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Wir rekrutieren kluge K\u00f6pfe und setzen uns f\u00fcr eine Kultur der gegenseitigen Unterst\u00fctzung und Inklusion ein. So k\u00f6nnen mit Ihren Ideen zu weltver\u00e4ndernden Innovationen und bahnbrechenden Technologien beitragen. Damit das m\u00f6glich ist, nutzen wir die ganze Breite und Tiefe unseres weltweiten Know-hows. Wir liefern Antworten, machen Komplexes einfach und \u00fcberwinden gemeinsam anspruchsvollste Herausforderungen.</p> <p><strong>Innovationen mit Technologieexperten<br /></strong>Karriere kennt keine Grenzen \u2013 davon sind wir bei Qualcomm fest \u00fcberzeugt. Nutzen Sie die einzigartige M\u00f6glichkeit, mit hoch angesehenen und f\u00fchrenden Engineering- und Technologieexperten der Branche zusammenzuarbeiten. Bei uns erleben Sie Lernen und berufliche Weiterentwicklung in einer v\u00f6llig neuen Dimension.</p> <p><strong>Gesund leben, gesund arbeiten<br /></strong>Dar\u00fcber hinaus haben Sie Zugang zu Programmen wie unseren kontinuierlichen Lern- und Weiterentwicklungsprogrammen, der Erstattung von Studiengeb\u00fchren und Mentoring, um Ihr grenzenloses Potenzial auszusch\u00f6pfen \u2013 au\u00dferdem haben Sie die M\u00f6glichkeit, Ihre Lebensqualit\u00e4t durch unsere umfassenden, erstklassigen Leistungsangebote zu verbessern .</p> <p>Die Arbeit, die wir bei Qualcomm leisten, hat Auswirkungen auf das Leben rund um den Globus \u2013 und Sie k\u00f6nnen ein Teil davon sein. Bewerben Sie sich noch heute und entfalten Sie Ihr volles Potenzial..</p>"}}}, "customContent": {"positionSections": [{"title": "Unlock Your Limitless Potential with Qualcomm", "body": "<p>Whether you&rsquo;re launching a new career or ready to explore what&rsquo;s next in the evolution of your talent and expertise, you&rsquo;re about to embark on a career growth journey like no other.</p> <p><strong>Bring out your best, with the best<br /></strong>Our employees make Qualcomm&rsquo;s success possible. We hire the brightest minds and foster a supportive, inclusive culture where your ideas have the power to contribute to world-changing innovations and breakthrough technologies. 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We have multiple roles in all Hardware disciplines. 2+ years Hardware Engineering experience or related work experience. 2+ years of work experience in ASIC/SoC Design Experienced in RTL design using Verilog / System Verilog. Experienced in Linting, CDC , LEC and preferably Low Power check tools. Experienced in database management flows with Clearcase/Clearquest. Knowledge of RTL and Gate-Level power analysis. Knowledge and experience of defining HW/FW interfaces. Knowledge of low power design techniques Ability to program effectively in Verilog, C/C++, Python, Perl Experience in unit and subsystem level verification. Worked on coverage driven constraint random verification. Strong in System Verilog, UVM, Test planning Sound experience in testbench (stimulus, agent, monitor, checker) development. Worked in the verification having c based reference model inside the testbench Exposure in scripting(perl, Python). Experience with STA on large SOC with multi-scenario timing closure. Experience with Timing ECO techniques and implementation. Knowledge of library cells and optimizations. Familiar with circuit modeling, transistor fundamentals and worst case corner selection. Solid understanding industry standard tools for synthesis, place & route and tapeout flows. Good communication skills to work with different teams to accurately describe issues and follow them through for completion. Experience in STA and timing closure of high-performance SOC designs in sub-micron technologies. Knowledge of all aspects of timing including noise, cross-talk and others. Knowledge of basic SoC architecture and HDL languages like Verilog. Minimum of 2+ years experience in the area of ASIC/DFT In depth knowledge of DFT concepts In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations Expertise in scripting languages such as perl, shell, etc. Experience in simulating test vectors Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TK, TetraMax) Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains- LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux - Perl/TCL fundamentals/scripting PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Hands on experience with FPGA design tools: Synplify, Vivado, XILINX ISE, Work experience in FPGA based design implementation. FPGA RTL coding(Verilog/VHDL/System Verilog), FPGA constraint setup, verification, synthesis, Place and route and timing closure. Hands-on experience in WIFI/Ethernet/PCIe/USB/Multimedia/UFS/ARM CPU/DDR4/LPDDR5 emulation. Exposure/working experience in acceleration emulation platforms like Veloce/Palladium simulation Gate level simulation/emulation bring up Familiar with hardware schematics and Lab tools to debug. Work closely with RTL Design/Validation and Software teams for bug/issue debug, support and build bring up in emulation platform. Scripting/programming skill in C/C++, Tcl, Perl/Python/csh will be added advantage Experience in SoC verification/ validation. System-On-Chip Pre-Silicon emulation and Post-Silicon ASIC Validation experience related to board bring up and debug Leadership quality, excellent communication, development and documentation of silicon test plans and guidelines for engineers. Ability to collaborate and coordinate cross teams and sites effectively. Familiarity with the following: Lauterbach Trace32 environment. Experience with assembly and C programming. Have hands on experience of SOC architecture, micro-processor verification, and silicon debug environment. Hands on experience of processor programming and simulation. Knowledge and experience with processor silicon In Circuit debuggers and design for debug techniques. Knowledge and experience on how to operate advanced logic analyzers, Advanced Oscilloscopes, Protocol Analyzers and power measurement equipment's. Supports the establishment of program goals and prioritizes deliverables under minimal supervision of Program Management stakeholders. Manages and takes responsibility for multiple small programs/technology with minimal complexity or a single program/technology with moderate complexity by applying up-to-date program management knowledge to meet deadlines. Builds and manages the execution of the Plan of Record (e.g., on time, on budget, within scope) for multiple small programs or a single medium sized program, which includes schedule and resource forecasting, stakeholder identification, method and frequency of communication, scope, and prioritization. Tracks all key metrics pertaining to a program, provides early warning for potential metric deviations and escalates in timely manner when metrics deviate significantly from Plan of Record. Coordinates the work of a small team on assigned tasks with guidance and maintains progress in tracking system. Identifies program issues/risks and creates a risk mitigation plan for multiple small programs or a single medium-sized program. Maintains and updates the risk tracker. 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