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Develop and maintain synthesis scripts and flows for hierarchical and flat designs. Collaborate with STA teams to resolve setup/hold violations. Apply physical-aware synthesis techniques to meet aggressive PPA targets. Implement low-power strategies using UPF/CPF flows. Work closely with RTL design, DFT, and physical design teams for seamless handoff. Provide feedback to architecture and RTL teams for QoR improvements. Perform LEC (Logical Equivalence Check), CLP (Clock/Power checks), and linting. Mentor junior engineers and drive best practices across synthesis and timing teams. Strong knowledge of ASIC design flow: RTL \u2192 Synthesis \u2192 STA \u2192 P&R. Proficiency in synthesis tools (Design Compiler, Genus) and STA tools (PrimeTime). Experience with UPF/CPF-based flows and multi-voltage designs. Ability to lead synthesis teams and coordinate with cross-functional groups. Bachelor's/Master's in Electrical Engineering, Computer Engineering, or related field. 8+ years in ASIC synthesis and timing closure, with at least 2 years in NPU or AI processor design. Experience with advanced nodes (5nm/3nm), hierarchical synthesis, and physical-aware flows. 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