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Bei uns erleben Sie Lernen und berufliche Weiterentwicklung in einer v\u00f6llig neuen Dimension.</p> <p><strong>Gesund leben, gesund arbeiten<br /></strong>Dar\u00fcber hinaus haben Sie Zugang zu Programmen wie unseren kontinuierlichen Lern- und Weiterentwicklungsprogrammen, der Erstattung von Studiengeb\u00fchren und Mentoring, um Ihr grenzenloses Potenzial auszusch\u00f6pfen \u2013 au\u00dferdem haben Sie die M\u00f6glichkeit, Ihre Lebensqualit\u00e4t durch unsere umfassenden, erstklassigen Leistungsangebote zu verbessern .</p> <p>Die Arbeit, die wir bei Qualcomm leisten, hat Auswirkungen auf das Leben rund um den Globus \u2013 und Sie k\u00f6nnen ein Teil davon sein. Bewerben Sie sich noch heute und entfalten Sie Ihr volles Potenzial..</p>"}}}, "customContent": {"positionSections": [{"title": "Unlock Your Limitless Potential with Qualcomm", "body": "<p>Whether you&rsquo;re launching a new career or ready to explore what&rsquo;s next in the evolution of your talent and expertise, you&rsquo;re about to embark on a career growth journey like no other.</p> <p><strong>Bring out your best, with the best<br /></strong>Our employees make Qualcomm&rsquo;s success possible. We hire the brightest minds and foster a supportive, inclusive culture where your ideas have the power to contribute to world-changing innovations and breakthrough technologies. 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Debug and resolve physical verification violations, working closely with layout, design, and CAD teams. Collaborate with foundries to ensure compliance with latest design rule manuals (DRMs) and tapeout checklists. Support signoff verification, including multi-corner/multi-mode analysis and ECO validation. Develop and maintain automation scripts for verification flows, reporting, and regression testing. Participate in design reviews, providing feedback on layout quality, rule compliance, and manufacturability. Ensure timely delivery of clean GDSII for tapeout, with full verification signoff. Perform full-chip and block-level static timing analysis (STA) using industry-standard tools (e.g., Synopsys PrimeTime, Cadence Tempus). Develop, validate, and maintain timing constraints (SDC) for multiple modes and corners. Collaborate with RTL, synthesis, and physical design teams to ensure timing-aware design practices. Analyze clock tree timing, including skew, latency, and jitter impacts. Support signoff timing verification, including cross-domain timing and false/multicycle path handling. Participate in design reviews, providing insights on timing risks and mitigation strategies. Develop and maintain power intent files (UPF/CPF) and ensure alignment with design specifications. Collaborate with RTL, synthesis, and physical design teams to integrate power-aware features such as power gating, retention, isolation, and level shifting. Perform power-aware static checks, simulation, and formal verification to validate power intent. Support signoff verification including power-aware LVS/DRC, STA, and EM/IR analysis. Participate in design reviews, providing insights on power architecture, risks, and mitigation strategies. Ensure compliance with foundry low-power guidelines and contribute to successful tapeout. Leverages expert ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products. Creates highly advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements. Collaborates with high-level representatives across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs. Serves as an expert resource for all aspects of the process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable highly advanced architecture and design of multiple complex blocks/SoC or IC Packages; provides technical expertise and support to team members. Writes detailed technical documentation for highly complex EDA/IP/ASIC projects; reviews technical documentation for experienced engineers. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 10+ years of experience in physical design, with a focus on clock tree design and implementation. Strong understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design. Proficiency with EDA tools for CTS, STA, and physical verification (e.g., ICC2, Innovus, PrimeTime). Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies. Solid scripting skills (TCL, Python, Perl) for flow automation and data analysis. Familiarity with low-power design techniques, including clock gating and multi-voltage domains. Experience with custom clock tree architectures such as H-tree, mesh, or spine-based topologies. Knowledge of EM/IR analysis, thermal-aware clocking, and reliability modeling. Exposure to high-speed interface clocking (e.g., SerDes, DDR, PCIe). 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